DARPA’s NanoWriter Could Bring Small-Lot, Custom ASICs Production to Reality


While commercial applications are driving miniaturization and computing power for personal communications, digital cameras and digital controllers used in modern automobiles and electrical appliances, defense electronics applications dictate the state of the art electronics in space, high precision navigation (GPS and inertial), and digital circuits performing massive processing for imaging, signal processing, high level encryption etc.

The huge cost difference between the commercially available components, such as Application Specific Integrated Circuits (ASIC) and their military specific equivalents brought developers of military equipment to rely on commercially available equipment, leading to certain compromises in reliability, or performance.

The new high-throughput maskless tool developed at DARPA, achieves high throughput through the simultaneous deployment of 1 million parallel electron beamlets. Illustration: DARPA

The primary cost factor associated with the high cost of these military components is the low production series used for development and serial production. Today’s Integrated Circuits (IC) are produced through complex lithographic processing batches, spanning over weeks. IC Lithography is currently performed by inserting a complex mask between a deep ultraviolet light source and a silicon wafer, projecting a circuit pattern onto that wafer.

“As feature sizes on integrated circuits have decreased to below 65 nanometers, the cost of these mask sets has become an overriding factor for small-lot fabrication of only a few wafers,” said Joseph Mangano, DARPA program manager. “By eliminating expensive mask sets, the Nanowriter tool will provide the cost benefits of large-scale IC manufacturing in quantities of one wafer.”

Small-batch applications suitable for military uses require an individual ‘painting’ of every IC through ‘direct drive’ lithography, one-by-one, rather than processing batches of millions at a time. However, high throughput in direct-write lithography is difficult to achieve since each feature is written serially as opposed to conventional lithography where millions of features are written in parallel.

To help meet a critical need for high-resolution lithography for cost-effective fabrication of application specific integrated circuits (ASIC), DARPA’s Maskless Nanowriter program is developing a massively parallel, direct-write electron-beam (eBeam) lithography tool with a write speed more than 100 times faster than current single-column eBeam tools. The program recently achieved two important milestones when it demonstrated a micro-lens array to pattern a beam into a million electron beamlets, and showed a second-generation eBeam column designed to significantly reduce pattern blur.

The new high-throughput maskless tool developed at DARPA, achieves high throughput through the simultaneous deployment of 1 million parallel electron beamlets. The new Nanowriter tool is targeted at the 45-nm lithography node with technology scalable to 32 nm and beyond. If successful, this program will eliminate the need for expensive mask sets and will increase economic viability of small-lot production for custom, ASICs and micro-electromechanical systems.